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document number: mc34712 rev. 4.0, 5/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. 3.0 a 1.0 mhz fully integrated ddr switch-mode power supply the 34712 is a highly integrated, s pace efficient, low cost, single synchronous buck switching regulator with integrated n-channel power mosfets. it is a high performance point-of-load (pol) power supply with the ability to track an external reference voltage. its high efficient 3.0 a sink and source capability combined with its voltage tracking/sequencing ability a nd tight output regulation, makes it ideal to provide the termination voltage (v tt ) for modern data buses such as double-data-rate (ddr) memory buses. it also provides a buffered output reference voltage (v ref ) to the memory chipset the 34712 offers the designer the flexibility of many control, supervisory, and protection functions to allow for easy implementation of complex designs. it is housed in a pb-free, thermally enhanced, and space efficient 24-pin exposed pad qfn. features ?45 m ? integrated n-channel power mosfets ? input voltage operating range from 3.0 v to 6.0 v ? 1 % accurate output voltage, ranging from 0.7 v to 1.35 v ? 1 % accurate buffered reference output voltage ? programmable switching frequency range from 200 khz to 1.0 mhz with a default of 1.0 mhz ? over current limit and short circuit protection ? thermal shutdown ? output overvoltage and undervoltage detection ? active low power good output signal ? active low standby and shutdown inputs ? pb-free packaging designated by suffix code ep. figure 1. 34712 simplified application diagram switch-mode power supply ep suffix 98arl10577d 24-pin qfn 34712 ordering information device temperature range (t a ) package mc34712ep/r2 -40 to 85c 24 qfn v in mcu pvin vrefin vin vddi freq gnd sd stby boot sw vout inv comp vrefout pgnd pg ddr memory controler 34712 v ddq ddr memory chipset v in v ref v tt v ddq v ddq memory bus terminating resistors (3.0v to 6.0v)
analog integrated circuit device data 2 freescale semiconductor 34712 internal block diagram internal block diagram figure 2. 34712 simplifi ed internal block diagram oscillator ramp ge ne ra to r system co nt ro l v bg freq pv in vddi vrefin vrefo ut gnd pg nd inv comp boo t i sense i se nse v b oot system reset pg sd error amplifier pwm comparator bu ffe r r ref1 r re f2 thermal monitoring discharge vout sw stby discharge disch ar ge m3 m1 current monit or in g m4 i li mit vin p ro g. fre qu en cy f sw buck cnt l. lo gi c ga te driver m2 internal vo l t a g e regulator v ddi bandgap regulator v ddi m5 m6 v in
analog integrated circuit device data freescale semiconductor 3 34712 pin connections pin connections figure 3. 34712 pin connections table 1. 34712 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 10 . pin number pin name pin function formal name definition 1 gnd ground signal ground analog signal ground of ic 2 freq passive frequency adjustment buck converter switching frequency adjustment pin 3 nc none no connect no internal connections to this pin 4 pg output power good active-low (open drain) power-good status reporting pin 5 stby input standby standby mode input control pin 6 s d input shutdown shutdown mode input control pin 7 vrefin input voltage-tracking- reference input voltage-tracking-reference voltage input 8 vrefout output reference voltage output buffered output equal to 1/2 of voltage-tracking reference 9 comp passive compensation buck converter external compensation network pin 10 inv input error amplifier inverting input buck converter error amplifier inverting input pin 11 vout output output voltage discharge fet discharge fet drain connection (connect to buck converter output capacitors) 12,13,14 pgnd ground power ground ground return for buck converter and discharge fet 15,16,17 sw power switching node buck converter power switching node 18,19,20 pvin supply power-circuit supply input buck converter main supply voltage input 21 boot passive bootstrap bootstrap switching node (connect to bootstrap capacitor) gnd freq stby pg nc sd vrefin comp inv vout pgnd sw pvin boot vin vddi vrefout pgnd pgnd sw sw pvin pvin vin transparent 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view
analog integrated circuit device data 4 freescale semiconductor 34712 pin connections 22,23 vin supply logic-circuit supply input logic circuits supply voltage input 24 vddi passive internal voltage regulator internal vdd regulator (connect fi lter capacitor to this pin) table 1. 34712 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 10 . pin number pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 34712 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings input supply voltage (vin) pin v in -0.3 to 7.0 v high-side mosfet drain voltage (pvin) pin pv in -0.3 to 7.0 v switching node (sw) pin v sw -0.3 to 7.5 v boot pin (referenced to sw pin) v boot - v sw -0.3 to 7.5 v pg , vout, sd , and stby pins - -0.3 to 7.0 v vddi, freq, inv, comp, vrefin, and vrefout pins - -0.3 to 3.0 v continuous output current (1) i out 3.0 a esd voltage (2) human body model device charge model (cdm) v esd1 v esd3 2000 750 v thermal ratings operating ambient temperature (3) t a -40 to 85 c storage temperature t stg -65 to +150 c peak package reflow temperature during reflow (4) , (5) t pprt note 5 c maximum junction temperature t j(max) +150 c power dissipation (t a = 85 c) (6) p d 2.9 w notes 1. continuous output current capability so long as t j is t j(max) . 2. esd1 testing is performed in accor dance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd3 testing is performed in accordance with the charge device model (cdm). 3. the limiting factor is junction temperature, taking into account power dissipation, ther mal resistance, and heatsinking. 4. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. freescale?s package reflow capability meets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. 6. maximum power dissipation at indicated ambient temperature.
analog integrated circuit device data 6 freescale semiconductor 34712 electrical characteristics maximum ratings thermal resistance (7) thermal resistance, junction to ambient, single-layer board (1s) (8) r ja 139 c/w thermal resistance, junction to am bient, four-layer board (2s2p) (9) r jma 43 c/w thermal resistance, junction to board (10) r jb 22 c/w notes 7. the pvin, sw, and gnd pins comprise the main heat conduction paths. 8. per semi g38-87 and jedec jesd51-2 with th e single-layer board (jesd51-3) horizontal. 9. per jedec jesd51-6 with the board (jesd51-7) horizontal. ther e are no thermal vias connecting the package to the two planes i n the board. 10. thermal resistance between the device and the printed circuit board per jedec jesd51- 8. board temperature is measured on the top surface of the board near the package. table 2. maximum ratings (continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data freescale semiconductor 7 34712 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit ic input supply voltage (vin) input supply voltage operating range v in 3.0 - 6.0 v input dc supply current (11) normal mode: sd = 1 & stby = 1, unloaded outputs i in - - 25 ma input dc supply current (11) standby mode, sd = 1 & stby = 0 i inq - - 15 ma input dc supply current (11) shutdown mode, sd = 0 & stby = x i inoff - - 100 a internal supply voltage output (vddi) internal supply voltage range v ddi 2.35 2.5 2.65 v buck converter (pvin, sw, gnd, boot, inv, comp) high-side mosfet drain voltage range p vin 2.5 - 6.0 v output voltage adjustment range (12) v out 0.7 - 1.35 v output voltage accuracy (12) , (13) , (14) - -1.0 - 1.0 % line regulation (12) normal operation, v in = 3.0 v to 6.0 v, i out = 3.0 a reg ln -1.0 - 1.0 % load regulation (12) normal operation, i out = -3.0 a to 3.0 a reg ld -1.0 - 1.0 % error amplifier common mode voltage range (12) , (15) v ref 0.0 - 1.35 v output undervoltage threshold v uvr -1.5 - -8.0 % output overvoltage threshold v ovr 1.5 - 8.0 % continuous output current i out -3.0 - 3.0 a over current limit, sinking and sourcing i lim - 4.0 - a short circuit current limit (sourcing and sinking) i short - 6.5 - a high-side n-ch power mosfet (m3) r ds(on) (12) i out = 1.0 a, v boot - v sw = 3.3 v r ds(on)hs 10 - 45 m ? low-side n-ch power mosfet (m4) r ds(on) (12) i out = 1.0 a, v in = 3.3 v r ds(on)ls 10 - 45 m ? notes 11. see section ?modes of operation?, page 14 has a detailed description of the different operating modes of the 34712 12. design information only, this parameter is not production tested. 13. 1% is assured at room temperature. 14. overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are rec ommended. 15. the 1% output voltage regulation is only guaranteed for a comm on mode voltage range greater than or equal to 0.7v at room temperature.
analog integrated circuit device data 8 freescale semiconductor 34712 electrical characteristics static electrical characteristics m2 r ds(on) (v in = 3.3 v, m2 is on) r ds(on)m2 1.5 - 4.0 ? pvin pin leakage current (standby and shutdown modes) i pvin -10 - 10 a inv pin leakage current i inv -1.0 - 1.0 a thermal shutdown threshold (16) t sdfet - 170 - c thermal shutdown hysteresis (16) t sdhyfet - 25 - c oscillator (freq) oscillator frequency adjusting reference voltage range v freq 0.0 - v ddi v tracking (vrefin, vrefout, vout) vrefin external reference voltage range (16) v refin 0.0 - 2.7 v vrefout buffered reference voltage range v refout 0.0 - 1.35 v vrefout buffered reference voltage accuracy (17) - -1.0 - 1.0 % vrefout buffered reference voltage current capability i refout 0.0 - 8.0 ma vrefout buffered reference voltage over current limit i refoutlim - 11 - ma vrefout total discharge resistance (16) r tdr(m6) - 50 - ? vout total discharge resistance (16) r tdr(m5) - 50 - ? vout pin leakage current (standby mode, v out = 3.6 v) i voutlkg -1.0 - 1.0 a control and supervisory ( stby , sd , pg ) stby high level input voltage v stbyhi 2.0 - - v stby low level input voltage v stbylo - - 0.4 v stby pin internal pull up resistor r stbyup 1.0 - 2.0 m ? sd high level input voltage v sdhi 2.0 - - v sd low level input voltage v sdlo - - 0.4 v sd pin internal pull up resistor r sdup 1.0 - 2.0 m ? pg low level output voltage (i pg = 3.0 ma) v pglo - - 0.4 v pg pin leakage current (m1 is off, pulled up to vin) i pglkg -1.0 - 1.0 a notes 16. design information only, this parameter is not production tested. 17. the 1 % accuracy is only guaranteed for v refout greater than or equal to 0.7 v at room temperature. table 3. static elec trical characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 34712 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit buck converter (pvin, sw, gnd, boot) switching node (sw) rise time (19) (p vin = 3.3 v, i out = 3.0 a) t rise - 14 - ns switching node (sw) fall time (19) (p vin = 3.3 v, i out = 3.0 a) t fall - 20 - ns soft start duration (normal mode) t ss 1.3 - 2.6 ms over current limit timer t lim - 10 - ms over current limit retry time-out period t timeout 80 - 120 ms output undervoltage/overvoltage filter delay timer t filter 5.0 - 25 s oscillator (freq) oscillator default switching frequency (18) (freq = gnd) f sw - 1.0 - mhz oscillator switching frequency range f sw 200 - 1000 khz control and supervisory ( stby , sd , pg ) pg reset delay t pgreset 8.0 - 12 ms thermal shutdown retry time-out period (19) t timeout 80 - 120 ms notes 18. oscillator frequency tolerance is 10%. 19. design information only, this parameter is not production tested.
analog integrated circuit device data 10 freescale semiconductor 34712 functional description introduction functional description introduction in modern microprocessor/memory applications, address commands and control lines requ ire system level termination to a voltage (v tt ) equal to 1/2 the memory supply voltage (v ddq ). having the termination voltage at midpoint, the power supply insures symmetry for switching times. also, a reference voltage (v ref ) that is free of any noise or voltage variations is needed for the ddr sdram input receiver, v ref is also equal to 1/2 v ddq . varying the v ref voltage will effect the setup and hold time of the memory. to comply with ddr requirements and to obtain best performance, v tt and v ref need to be tightly regulated to track 1/2 v ddq across voltage, temperature, and noise margins. v tt should track any variations in the dc v ref value (v tt = v ref +/- 40 mv), (see figure 4 ) for a ddr system level diagram. the 34712 supplies the v tt and a buffered v ref output. to ensure compliance with ddr specifications, the v ddq line is applied to the vrefin pin and divided by 2 internally through a precision resistor divider. this internal voltage is then used as the reference voltage for the v tt output. the same internal voltage is also buffered to give the v ref voltage at the vrefout pin for the application to use without the need for an external resistor divider. the 34712 provides the tight voltage regulation and power sequencing/tracking required along with handling the ddr peak transient current requirements. buffering the v ref output helps its immunity against noise and load changes. the 34712 utilizes a voltage mode synchronous buck switching converter topology with integrated low r ds(on) (45 m ? ) n-channel power mosfets to provide a v tt voltage with an accuracy of less than 2.0 %. it has a programmable switching frequency that allows for flexibility and optimization over the operating conditions and can operate at up to 1.0 mhz to significantly reduce the external components size and cost. the 34712 can sink and source up to 3.0 a of continuous current. it provides protection against output over current, overvoltage, undervolt age, and overtemperature conditions. it also protects the system from short circuit events. it incorporates a power- good output signal to alert the host when a fault occurs. for boards that support the suspend-to-ram (s3) and the suspend-to-disk (s5) states, the 34712 offers the stby and the sd pins respectively. pulling any of these pins low, puts the ic in the corresponding state. by integrating the control/su pervisory circuitry along with the power mosfet switches for the buck converter into a space-efficient package, the 34712 offers a complete, small- size, cost-effective, and simple solution to satisfy the needs of ddr memory applications. besides ddr memory termination, the 34712 can be used to supply termination for other active buses and graphics card memory. it can be used in netcom/telecom applications like servers. it can also be used in desktop motherboards, game consoles, set top boxes, and high end high definition tvs. figure 4. ddr system level diagram functional pin description reference voltage input (vrefin) the 34712 will track 1/2 the voltage applied at this pin. reference voltage output (vrefout) this is a buffered reference vo ltage output that is equal to 1/2 v refin . it has a 10.0 ma current drive capability. this output is used as the v ref voltage rail and should be filtered against any noise. connect a 0.1 f, 6 v low esr ceramic filter capacitor between th is pin and the gnd pin and between this pin and v ddq rail. v refout is also used as the reference voltage for the buck converter error amplifier. frequency adjustme nt input (freq) the buck converter switching frequency can be adjusted by connecting this pin to an external resistor divider between vddi and gnd pins. the default switching frequency (freq pin connected to ground, gnd) is set at 1.0 mhz. signal ground (gnd) analog ground of the ic. internal analog signals are referenced to this pin voltage. v ddq v ddq v tt v ref bus ddr memory controller ddr memory input receiver r s r t
analog integrated circuit device data freescale semiconductor 11 34712 functional description functional pin description internal supply voltage output (vddi) this is the output of the internal bias voltage regulator. connect a 1.0 f, 6 v low esr ceramic filter capacitor between this pin and the gnd pin. filtering any spikes on this output is essential to the inte rnal circuitry stable operation. output voltage disc harge path (vout) output voltage of the buck conv erter is connected to this pin. it only serves as the output discharge path once the sd signal is asserted. error amplifier inverting input (inv) buck converter error amplifier inverting input. connect the vtt voltage directly to this pin. compensation input (comp) buck converter external compensation network connects to this pin. use a type iii compensation network. input supply voltage (vin) ic power supply input voltage. input filtering is required for the device to operate properly. power ground (pgnd) buck converter and discharge mosfets power ground. it is the source of the buck converter low-side power mosfet. switching node (sw) buck converter switching node. this pin is connected to the output inductor. power input voltage (pvin) buck converter power input voltage. this is the drain of the buck converter high-side power mosfet. bootstrap input (boot) bootstrap capacitor input pin. connect a capacitor (as discussed on page 19 ) between this pin and the sw pin to enhance the gate of the high-side power mosfet during switching. shutdown input ( sd ) if this pin is tied to the gnd pin, the device will be in shutdown mode. if left unconnect ed or tied to the vin pin, the device will be in normal mode. the pin has an internal pull up of 1.5 m ? . this input accepts the s5 (suspend-to-disk) control signal. standby input ( stby ) if this pin is tied to the gnd pin, the device will be in standby mode. if left unconnected or tied to the vin pin, the device will be in normal mode. the pin has an internal pull up of 1.5 m ? . this input accepts the s3 (suspend-to-ram) control signal. power good output signal ( pg ) this is an active low open drain output that is used to report the status of the device to a host. this output activates after a successful power up sequence and stays active as long as the device is in normal operation and is not experiencing any faults. this output activates after a 10 ms delay and must be pulled up by an external resistor to a supply voltage (e.g.,v in .).
analog integrated circuit device data 12 freescale semiconductor 34712 functional description functional internal block description functional internal block description figure 5. 34712 internal block diagram internal bias circuits this block contains all circui ts that provide the necessary supply voltages and bias currents for the internal circuitry. it consists of: ? internal voltage supply regulator: this regulator supplies the v ddi voltage that is used to drive the digital/ analog internal circuits. it is equipped with a power-on- reset (por) circuit that watc hes for the right regulation levels. external filtering is needed on the vddi pin. this block will turn off during the shutdown mode. ? internal bandgap reference voltage: this supplies the reference voltage to some of the internal circuitry. ? bias circuit: this block generates the bias currents necessary to run all of the blocks in the ic. system control and logic this block is the brain of the ic where the device processes data and reacts to it . based on the status of the stby and sd pins, the system control reacts accordingly and orders the device into the right status. it also takes inputs from all of the monitoring/prot ection circuits and initiates power up or power down commands. it communicates with the buck converter to manage the switching operation and protects it against any faults. oscillator this block generates the clock cycles necessary to run the ic digital blocks. it also generates the buck converter switching frequency. the switching frequency has a default value of 1.0 mhz and can be programmed by connecting a resistor divider to the freq pin, between vddi and gnd pins (see figure 1 ). protection functions this block contains the following circuits: ? over current limit and short circuit detection: this block monitors the output of the buck converter for over current conditions and short circuit events and alerts the system control for further command. ? thermal limit detection: this block monitors the temperature of the device for overheating events. if the temperature rises abov e the thermal shutdown threshold, this block will alert the system control for further commands. ? output overvoltage and undervoltage monitoring: this block monitors the buck converter output voltage to ensure it is within regulation boundaries. if not, this block alerts the system co ntrol for furt her commands. control and supervisory functions this block is used to interface with an outside host. it contains the following circuits: ? standby control input: an outside host can put the 34712 device into standby mode (s3 or suspend-to- ram mode) by sending a logic ?0? to the stby pin. ? shutdown control input: an outside host can put the 34712 device into shutdown mode (s5 or suspend-to- disk mode) by sending a logic ?0? to the sd pin. ? power good output signal pg : the 34712 can communicate to an external host that a fault has internal bias system control oscillator circuits & logic control & protection tracking & supervisory functions functions sequencing buck converter
analog integrated circuit device data freescale semiconductor 13 34712 functional description functional internal block description occurred by releasing the drive on the pg pin high, allowing the signal/pin to be pulled high by the external pull-up resistor. tracking and sequencing this block allows the output of the 34712 to track 1/2 the voltage applied at the vrefin pin. this allows the v ref and v tt voltages to track 1/2 v ddq and assures that none of them will be higher than v ddq at any point during normal operating conditions. for power down during a shutdown (s5) mode, the 34712 uses internal discharge mosfets (m5 and m6 on figure 2 ) to discharge v tt and v ref respectively. these discharge mosfets are only active during shutdown mode. using this block along with controlling the sd and stby pins can offer the user power sequencing capabilities by controlling when to turn the 34712 outputs on or off. buck converter this block provides the main function of the 34712: dc to dc conversion from an un-regulated input voltage to a regulated output voltage used by the loads for reliable operation. the buck converter is a high performance, fixed frequency (externally adjustable), synchronous buck pwm voltage-mode control. it drives integrated 45 m ? n-channel power mosfets saving board space and enhancing efficiency. the switching regulator output voltage is adjustable with an accuracy of less than 2.0 % to meet ddr requirements. its output has the ab ility to track 1/2 the voltage applied at the vrefin pin. the regulator's voltage control loop is compensated using a type iii compensation network, with external components to allow for optimizing the loop compensation, for a wide range of operating conditions. a typical bootstrap circuit with an internal pmos switch is used to provide the voltage necessary to properly enhance the high-side mosfet gate. the 34712 is designed to address ddr memory power supplies. the integrat ed converter has the ability to both sink and source up to 3.0 a of continuous current, making it suitable for bus termination power supplies.
analog integrated circuit device data 14 freescale semiconductor 34712 functional device operation operational modes functional device operation operational modes figure 6. operation modes diagram modes of operation the 34712 has three primar y modes of operation: normal mode in normal mode, all functions and outputs are fully operational. to be in this mode, the v in needs to be within its operating range, both shutdown and standby inputs are high, and no faults are presen t. this mode consumes the most amount of power. standby mode this mode is predominantly used in desktop memory solutions where the ddr supply is desired to be acpi compliant (advanced configuration and power interface). when this mode is activated by pulling the stby pin low, v tt is put in high z state, i out = 0 a, and v ref stays active. this is the s3 state suspend-to-ram or self refresh mode and it is the lowest dram power state. in this mode, the dram will preserve the data. while in this mode, the 34712 consumes less power than in the normal mode, because the buck converter and most of the internal blocks are disabled. shutdown mode in this mode, activated by pulling the sd pin low, the chip is in a shutdown state and the outputs are all disabled and discharged. this is the s4/s 5 power state or suspend-to- disk state, where the dram will loose all of its data content (no power supplied to the dram). the reason to discharge the v tt and v ref lines is to ensure upon exiting, the shutdown mode that v tt and v ref are lower than v ddq , otherwise v tt can remain floating high, and be higher than v ddq upon powering up. in this mode, the 34712 consumes the least amount of power since almost all of the internal blocks are disabled. start-up sequence when power is first applied, the 34712 checks the status of the sd and stby pins. if the device is in a shutdown mode, no block will power up and the output will not attempt to ramp. if the device is in a standby mode, only the v ddi internal supply voltage and the bias currents are established and no further activities will occur. once the sd and stby pins are released to enable the device, the internal v ddi por signal is also released. the rest of the internal blocks will be enabled shutdown v tt = discharge v ref = discharge standby v tt = off v ref = on 3.0v < = v in < = 6.0v power off v tt = off v ref = off v in < 3.0v normal v tt = on v ref = on thermal shutdown v tt = off v ref = off undervoltage v tt = on v ref = on overvoltage v tt = on v ref = on over current v tt = off v ref = on t j > = 170 c v tt < v uv v tt > v ov short circuit v tt = off v ref = off i out > = i lim for > = 10ms i out > = i short v tt > v uv v tt < v ov t j < = 145 c & t timeout expired t timeout expired t timeo ut expired sd = 0 & stby = x sd = 1 & stby = 1 pg = 1 pg = 0 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 sd = 1 & stby = 1 sd = 1 & stby = 0 shutdown v tt = discharge v ref = discharge standby v tt = off v ref = on 3.0v < = v in < = 6.0v power off v tt = off v ref = off v in < 3.0v normal v tt = on v ref = on thermal shutdown v tt = off v ref = off undervoltage v tt = on v ref = on overvoltage v tt = on v ref = on over current v tt = off v ref = on t j > = 170 c v tt < v uv v tt > v ov short circuit v tt = off v ref = off i out > = i lim for > = 10ms i out > = i short v tt > v uv v tt < v ov t j < = 145 c & t timeout expired t timeout expired t timeo ut expired sd = 0 & stby = x sd = 0 & stby = x sd = 1 & stby = 1 sd = 1 & stby = 1 pg = 1 pg = 1 pg = 0 pg = 0 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 pg = 1 sd = 1 & stby = 1 sd = 1 & stby = 1 sd = 1 & stby = 0 sd = 1 & stby = 0
analog integrated circuit device data freescale semiconductor 15 34712 functional device operation protection and di agnostic features and the buck converter switching frequency value is determined by reading the freq pin. a soft start cycle is then initiated to ramp up the output of the buck converter (v tt ). the buck converter error amplifier uses the voltage on the vrefout pin (v ref ) as its reference voltage. v ref is equal to 1/2 v ddq , where v ddq is applied to the vrefin pin. this way, the 34712 assures that v ref and v tt voltages track 1/2 v ddq to meet ddr requirements. soft start is used to prev ent the output voltage from overshooting during startup. at initial startup, the output capacitor is at zero volts; v out = 0 v. therefore, the voltage across the inductor will be pv in during the capacitor charge phase which will create a very sharp di/dt ramp. allowing the inductor current to rise too high can result in a large difference between the charging current and the actual load current that can result in an undesired voltage spike once the capacitor is fully charged. the soft start is active each time the ic goes out of standby or shutdown mode, power is recycled, or afte r a fault retry. to fully take advantage of soft starting, it is recommended not to enable the 34712 output before introducing vddq on the vrefin pin. if this happens after a soft start cycle expires and the vrefin voltage has a high dv/dt, the output will naturally track it immediately and ramp up with a fast dv/dt itself and that will de feat the purpose of soft starting. for reliable operation, it is best to have the vddq voltage available before enabling the output of the 34712. after a successful start-up cycle where the device is enabled, no faults have occurr ed, and the output voltage has reached its regulation point, the 34712 pulls the power good output signal low after a 10 ms reset delay, to indicate to the host that the device is in normal operation. protection and diagnostic features the 34712 monitors the application for several fault conditions to protect the load fr om overstress. the reaction of the ic to these faults ranges from turning off the outputs to just alerting the host that something is wrong. in the following paragraphs, each fault c ondition is explained: output overvoltage an overvoltage condition o ccurs once the output voltage goes higher than the rising overvoltage threshold (v ovr ). in this case, the power good output signal is pulled high, alerting the host that a fault is present, but the v tt and v ref outputs will stay active. to avoid erroneous overvoltage conditions, a 20 s filter is implemented. th e buck converter will use its feedback loop to attempt to corre ct the fault. once the output voltage falls below the falling overvoltage threshold (v ovf ), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. output undervoltage an undervoltage condition occurs once the output voltage falls below the falling undervoltage threshold (v uvf ). in this case, the power good output signal is pulled high, alerting the host that a fault is present, but the v tt and v ref outputs will stay active. to avoid erroneous undervoltage conditions, a 20 s filter is implemented. th e buck converter will use its feedback loop to attempt to corre ct the fault. once the output voltage rises above the rising undervoltage threshold (v uvr ), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. output over current this block detects over current in the power mosfets of the buck converter. it is co mprised of a sense mosfet and a comparator. the sense mosfet acts as a current detecting device by sampling a ratio of the load current. that sample is compared via the comparator with an internal reference to determine if the outpu t is in over current or not. if the peak current in the outpu t inductor reaches the over current limit (i lim ), the converter will start a cycle-by-cycle operation to limit the current, and a 10 ms over current limit timer (t lim ) starts. the converter will stay in this mode of operation until one of the following occurs: ? the current is reduced back to the normal level before t lim expires, and in this case normal operation is regained. ?t lim expires without regaining normal operation, at which point the device turns off the output and the power good output signal is pulled high. at the end of a time-out period of 100 ms (t timeout ), the device will attempt another soft start cycle. ? the device reaches the thermal shutdown limit (t sdfet ) and turns off the output. the power good output signal is pulled high. short circuit current limit this block uses the same cu rrent detection mechanism as the over current limit detection block. if the load current reaches the i short value, the device reacts by shutting down the output immediately. this is necessary to prevent damage in case of a permanent short circuit. then, at the end of a time-out period of 100 ms (t timeout ), the device will attempt another soft start cycle. thermal shutdown thermal limit detection block monitors the te mperature of the device and protects agains t excessive heat ing. if the temperature reaches the thermal shutdown threshold (t sdfet ), the converter output switches off and the power good output signal indicates a fault by pulling high. the device will stay in this st ate until the temperature has decreased by the hysteresis value and then after a time-out period (t timeout ) of 100 ms, the device will retry automatically and the output will go through a soft start cycle. if successful normal operation is regained, the power good output signal is asserted low to indicate that.
analog integrated circuit device data 16 freescale semiconductor 34712 typical applications protection and di agnostic features typical applications vrefin vrefout vin sd stby freq vin sw vout vddi boot inv comp vout pvin pvin led sw vin inv comp pvin vmaster led vrefin vrefin stby sd vmaster vrefin gnd vin pvin gnd vmaster vout freq vddi vout vout pg pg sw vrefin vrefin compensation network pvin capacitors buck converter vin capacitors pgood led vmaster optional nopop i/o signals jumpers gnd gnd c4 100uf c4 100uf c19 1.9nf c19 1.9nf r1 20k r1 20k stby stby r16 4.7_nopop r16 4.7_nopop c18 0.02nf c18 0.02nf vrefin vrefin r2 12.7k_nopop r2 12.7k_nopop c17 10uf c17 10uf r7 1k r7 1k c11 0.1uf c11 0.1uf comp comp vout vout c7 100uf c7 100uf l1 1.5uh l1 1.5uh 1 2 u1 mc34712 u1 mc34712 boot 21 vin 22 vin 23 vddi 24 sgnd 1 stby 5 pg 4 freq 2 n/c 3 sd 6 vrefin 7 vrefout 8 vout 11 comp 9 inv 10 gnd 12 gnd 13 gnd 14 sw 15 sw 16 pvin 20 pvin 19 sw 17 pvin 18 vout2 vout2 r14 300 r14 300 r6 pot_50k_nopop r6 pot_50k_nopop vout1 vout1 c13 0.1uf c13 0.1uf vin vin c1 0.1uf c1 0.1uf r15 15k r15 15k c3 100uf c3 100uf pvin pvin r9 10k_nopop r9 10k_nopop d1 led d1 led pg pg c14 0.1uf c14 0.1uf sd sd c15 0.1uf c15 0.1uf c16 0.1uf c16 0.1uf freq freq j3 j3 1 2 3 sd sd 1 2 vrefout vrefout r11 10k r11 10k r3 4.7_nopop r3 4.7_nopop c6 100uf c6 100uf inv inv r12 10k_nopop r12 10k_nopop j2 j2 1 2 3 c8 100uf c8 100uf r8 10k_nopop r8 10k_nopop c9 1nf_nopop c9 1nf_nopop d2 pmeg2010ea_nopop d2 pmeg2010ea_nopop j1 con10a j1 con10a 1 2 3 4 5 6 7 8 9 10 stby stby 1 2 boot boot c2 1uf c2 1uf c12 0.1uf c12 0.1uf c5 100uf c5 100uf sw sw c20 1nf c20 1nf vddi vddi
analog integrated circuit device data freescale semiconductor 17 34712 typical applications protection and di agnostic features component selection switching frequency selection the switching frequency defaults to a value of 1.0 mhz when the freq pin is grounded, and 200 khz when the freq pin is connected to vddi. intermediate switching frequencies can be obtained by connecting an external resistor divider to the freq pin. the table below shows the resulting switching frequency versus freq pin voltage. table 5. switching frequency adjustment figure 7. resistor divider for frequency adjustment selection of the inductor inductor calculation is straight forward, being where, maximum off time percentage switching period. drain ? to ? source resistance of fet winding resistan ce of inductor output current ripple. output filter capacitor for the output capacitor, the following considerations are more important than the act ual capacitance value, the physical size, the esr and the voltage rating: transient response percentage, tr_% maximum transient voltage, tr_v_dip = vo*tr_% maximum current step, inductor current rise time, where, d_max = maximum on time percentage. i o = rated output current. vin_min = minimum input voltage at pv in as a result, it is possible to calculate frequency voltage applied to pin freq 200 2.341 ? 2.500 253 2.185 - 2.340 307 2.029 - 2.184 360 1.873 - 2.028 413 1.717 ? 1.872 466 1.561 ? 1.716 520 1.405 - 1.560 573 1.249 - 1.404 627 1.093 - 1.248 680 0.936 - 1.092 733 0.781 - 0.936 787 0.625 - 0.780 840 0.469 - 0.624 893 0.313 - 0.468 947 0.157 - 0.312 1000 0.000 - 0.156
analog integrated circuit device data 18 freescale semiconductor 34712 typical applications protection and di agnostic features in order to find the maximum allowed esr, the effects of the esr is ofte n neglected by the designers and may present a hidden danger to the ultimate supply stability. poor quality capacitors have widely disparate esr value, which can make the closed loop response inconsistent. figure 8. transient parameters type iii compensation network power supplies are desired to offer accurate and tight regulation output voltages. to accomplish this requires a high dc gain. but with high gain comes the possibility of instability. the purpose of adding compensation to the internal error amplifier is to counteract some of the gains and phases contained in the control-to-out put transfer function that could jeopardized the stability of the power supply. the type iii compensation network used for 34712 comprises two poles (one integrator and one high frequency pole to cancel the zero generated from the esr of the output capacitor) and two zeros to cancel the two poles generated from the lc filter as shown in figure 9 . figure 9. type iii compensation network consider the crossover frequency, f cross , of the open loop gain at one-sixth of t he switching frequency, f sw. then, where r o is a user selected resistor. knowing the lc frequency, it can be obtained the values of r f and c s : this gives as a result, io worst case assumption current response dt_i_rise io_step + ? + ? f sw gate driver pwm comparitor v refout ramp generator error amplifier sw vout inv comp l r s c s r o c o c x r f c f 34712 ? &
analog integrated circuit device data freescale semiconductor 19 34712 typical applications protection and di agnostic features calculate rs by placing the pole 1 at the esr zero frequency: equating the pole 2 at crossover frequency to achieve a faster response and a proper phase margin, bootstrap capacitor the bootstrap capacitor is needed to supply the gate voltage for the high side mosfet. this n-channel mosfet needs a voltage difference between its gate and source to be able to turn on. the high side mosfet source is the sw node, so it is not ground and it is floating and moving in voltage, so we cannot just appl y a voltage directly to the gate of the high side that is referenced to ground, we need a voltage referenced to the sw node. that is why the bootstrap capacitor is needed for. this capacitor charges during the high side off time, since the low side will be on during that time, so the sw node and t he bottom of the bootstrap capacitor will be connected to ground and the top of the capacitor will be connected to a voltage source, so the capacitor will charge up to that voltage source (say 5v). now when the low side mosfet switches off and the high side mosfet switches on, the sw nodes rises up to vin, and the voltage on the boot pin will be vcap + vin. so the gate of the high side will have vcap across it and it will be able to stay enhanced. a 0.1 f capacitor is a good value for this bootstrap element. ? ?
analog integrated circuit device data 20 freescale semiconductor 34712 packaging packaging dimensions packaging packaging dimensions ep suffix 24 -pin plastic package 98arl10577d issue b
analog integrated circuit device data freescale semiconductor 21 34712 packaging packaging dimensions ep suffix 24 -pin plastic package 98arl10577d issue b
analog integrated circuit device data 22 freescale semiconductor 34712 revision history revision history revision date description of changes 1.0 2/2006 ? pre-release version ? implemented revision history page 2.0 11/2006 ? initial release ? converted format from market assessment to product preview ? major updates to the data, form, and style 3.0 2/2007 ? replaced all electrolytic c apacitors with ceramic ones in figure 1 ? deleted deadtime in dynamic electrical characteristics ? moved figures 8 ahead of type iii compensation network 4.0 5/2007 ? changed features fom 2% to 1% ? changed 34712 simplified application diagram ? removed machine model in maximum ratings ? added minimum limits to input dc supply current (11) normal mode, input dc supply current (11) standby mode, and input dc supply current (11) shutdown mode ? added high-side mosfet drain voltage range ? changed output voltage accuracy (12) , (13) , (14) ? changed short circuit current limit ? changed high-side n-ch power mosfet (m3) rds(on) (12) and low-side n-ch power mosfet (m4) rds(on) (12) ? changed m2 rds(on) ? changed pvin pin leakage current ? changed vrefout buffered reference voltage accuracy (17) , vrefout buffered reference voltage current capability , and vrefout buffered reference voltage over current limit ? changed stby pin internal pull up resistor and sd pin internal pull up resistor ? changed soft start duration , over current limit retry time-out period , and output undervoltage/ overvoltage filter delay timer ? changed oscillator default switching frequency (18) ? changed pg reset delay and thermal shutdown retry time-out period (19) ? changed drawings in typical applications ? changed drawing in type iii compensation network ? removed pc34712ep/r2 from the ordering information and added mc34712ep/r2 ? changed the data sheet status to advance information
mc34712 rev. 4.0 5/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should a buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, the buyer shall i ndemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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